Senior Staff Engineer – Static Timing Analysis (STA)

📋 Description

• Lead block-level and full-chip Static Timing Analysis (STA) across modes/corners using MMMC.
• Drive timing closure and signoff with Synthesis, CTS, P&R, extraction, and ECO teams.
• Define timing constraints, SDCs, and timing requirements; manage timing exceptions.
• Drive ECOs and timing optimization balancing PPA objectives.
• Collaborate to achieve robust timing convergence and timely tapeout.
• Contribute to automation, methodology improvements, and productivity gains.

🎯 Requirements

• 10+ years of experience in STA, timing closure, or related semiconductor roles.
• Bachelor's or Master's in Electronics, Electrical Engineering, VLSI, or related field.
• Strong knowledge of STA concepts: OCV, AOCV, POCV, signal integrity/noise, clocking, timing
• Hands-on with Synopsys PrimeTime and advanced timing signoff.
• Understanding of semiconductor flow: synthesis, CTS, P&R, extraction, ECOs.
• Proven ability to drive timing closure across designs and modes; strong scripting (Tcl, Python

🎁 Benefits

• Remote work option in India with hybrid/on-site Bengaluru when applicable.
• Opportunity to work on advanced semiconductor/AI/HPC infra.
• Exposure to complex SoC designs and timing signoff challenges.
• High level of technical ownership and influence over STA workflows.
• Fast-moving environment with emphasis on engineering execution and automation.
• Collaboration within a globally distributed engineering org; focus on productivity and ownership.