Senior Staff Engineer - Design Verification

📋 Description

• Define verification strategies for PCIe, CXL, Ethernet, and UCIe across IP/SoC subsystems.
• Architect reusable UVM testbenches, environments, agents, components for protocol verification.
• Verify PCIe Gen5/Gen6, CXL 3.x, Ethernet 200G/400G, UCIe PHY/Adapter layers for functionality and
• Lead coverage-driven verification, assertions, metrics analysis, coverage closure, sign-off.
• Lead debug across simulation, emulation, prototyping, silicon bring-up.
• Collaborate with design, architecture, validation, and other teams to deliver robust IP/SoC

🎯 Requirements

• Bachelor’s or Master’s in Electrical/Computer Engineering or related field.
• 12+ years in design verification with complex SoC/IP exposure.
• Proven verification architectures for high-speed interconnects.
• Hands-on SystemVerilog, UVM, coverage-driven verification, SystemVerilog Assertions (SVA).
• Deep knowledge of PCIe Gen5/Gen6, CXL 3.x, Ethernet 200G/400G, or similar high-speed protocols
• Strong SoC architecture understanding, IP integration, and verification methodologies.

🎁 Benefits

• Remote work: Remote position available for candidates based in India.
• Location: Bengaluru-based opportunity within a growing engineering team.
• Technical impact: Work on chiplet infrastructure and high-speed interconnects for AI/HPC.
• Ownership: Significant autonomy to shape verification strategies and roadmaps.
• Innovation: Work on advanced semiconductor challenges at chiplets and AI infrastructure
• Global collaboration: Distributed international engineering team.